HBM and DRAM Supply: When Will the Next Memory Glut Hit?

The memory industry is still in a shortage that producers have pre-sold through 2028–29. The first year a glut is even mechanically possible is 2029, and only if several greenfield waves land together while AI bit growth slows. The nearer risk is NAND, not DRAM/HBM.

The binding constraint is wafers, not announcements

HBM does not add bits in proportion to the cleanroom space it consumes. TrendForce’s published path has HBM taking about 18% of DRAM wafer starts at end-2025, about 22% in 2026, and about 30% by late 2027, while delivering only about 8%, 9%, and 13% of DRAM bits. The mechanism is a roughly 3× wafer-area penalty versus DDR of similar density, heading toward 4× as HBM4/HBM4E die sizes grow. Every incremental HBM wafer is taken out of the conventional DRAM pool until new cleanrooms exist. Samsung’s own comment matches that: HBM near 30% of industry DRAM wafer capacity in 2027, up from about 20%, with its own HBM starts rising from roughly 180,000 wafers a month in 2026 to about 250,000 in 2027. [1] [2] [3]

That is why sold-out language and new-fab press releases can both be true. On late-October earnings calls, Samsung said 2027 HBM is fully booked and tightness runs into 2028, with a target of locking 60–70% of capacity under long-term agreements through 2030. SK hynix said LTAs with 14 customers already cover more than half of 2027–28 capacity, customer HBM requests are more than double supply, and combining signed volume with negotiations still in process leaves DRAM and HBM effectively sold out through 2029, with imbalance expected through 2030. Micron has most of 2027 HBM contracted, more than 75% of calendar-2027 output committed, and told investors calendar 2027 and 2028 will be tighter than 2026, with no line of sight to balance. Jensen Huang, in an October 22, 2026 CNBC interview, said he sees no memory glut through 2029. [4] [5] [6] [7] [8]

For anyone trying to underwrite supply, the useful unit is qualified commercial wafers after yield and customer qualification, not groundbreaking dates. Tool lead times have stretched toward six to eight months, so a 2027 cleanroom opening is a 2028 bit story.

Where the new fabs actually land

The Big Three’s greenfield calendar clusters in two waves: a thin 2027 slice, then a much larger 2H28–2030 stack. CSIS’s September 2026 assessment frames the same shape: limited additions in 2026, more meaningful expansion in 2027, and a post-2028 wave large enough to either end the shortage or recreate a glut. [9]

Micron is the most geographically spread. First output is packaging and a mid-2027 wafer start, not a 2026 flood.

• Singapore HBM packaging: initial production early 2027, about $7 billion through the end of the decade. A second Taichung HBM packaging line opened in October 2026.
• Idaho ID1 DRAM wafers around mid-2027; Tongluo (acquired from Powerchip) around the same window, with more meaningful HBM/DRAM shipments into 2028.
• Gap, then 2H28: Idaho ID2, Hiroshima expansion, and a Singapore NAND wafer fab.
• Hiroshima: groundbreaking July 2026, about $9.3 billion, equipment from 2H28, commercial shipments around summer 2028, aimed at HBM and 1γ DRAM.
• Clay, New York: first production around 2030 inside a multi-fab complex planned in phases through the 2040s. CSIS cites an eventual ~200,000 wafers per month for the first Boise fab at full run-rate late in the decade, with a second Boise fab of similar scale planned. [10] [9] [11] [12] [13]

SK hynix has the earliest cleanroom date and the slowest path from cleanroom to full output.

• M15X in Cheongju is the near-term HBM4 lever: operating in 2H26, industry estimates around 40,000 wafers per month initially and about 80,000 in 2027, with management pushing it to maximum by end-2026.
• Yongin Y1 first cleanroom pulled forward to February 2027 from May. Ramp estimates diverge and should not be averaged. Supplier briefings describe six cleanrooms at 60,000 wafers per month every six months, implying a full Y1 near 360,000 by 1H30. CSIS is more conservative: 150,000 wafers per month by end-2028. LS Securities sits in between (about 60,000 in 2027, 180,000 in 2028, 300,000 in 2029).
• Y2: groundbreaking July 2027, first cleanroom June 2029, investment cited at 35.2 trillion won ($26.5 billion). M17 NAND cleanroom targeted for December 2028. Indiana HBM packaging is a 2H29 story, not a 2027 one. [14] [15] [16] [9]

Samsung is converting existing Pyeongtaek lines now and starting the big shell later.

• P5 tool move-in is being discussed for 2Q27 rather than 3Q27, with operations targeted in 2028 and an eventual 100,000–120,000 wafers per month on CSIS’s reading, biased to HBM and 1c DRAM. The shell is being redesigned as a triple-deck fab, which raises ultimate capacity but does not pull first wafers forward.
• First Yongin National Industrial Complex fab is now targeted for 2029 operation, one to two years earlier than the old plan. Six Yongin fabs and two Honam fabs are on the long roadmap; they are not 2027–28 supply. [10] [17] [18]

SEMI’s October 2026 symposium forecast is the clean industry-level check: global DRAM capacity, in 8-inch equivalents, from 2.08 million wafers per month last year to 2.94 million in 2030, up 41%, a 7.1% CAGR, concentrated in ≤15 nm. That is steady compounding, not a 2027 step-function. SEMI also warned that HBM’s extra wafer and back-end intensity can leave both advanced and legacy DRAM short even while headline capacity rises. [19]

What this means for a competitor or a buyer: 2027 is a conversion-and-packaging year. The first year multiple new DRAM shells contribute at once is 2028, and full run-rate is 2029–31. Anyone modeling a 2027 glut is modeling announcements, not wafers.

China adds commodity bits, not a global HBM reset

CXMT is now a real fourth DRAM supplier and still a non-factor in merchant HBM outside China.

Counterpoint put CXMT at about 9.5% of global DRAM revenue in 2Q26 and about 9–10% around 3Q26, fourth behind Samsung, SK hynix, and Micron. Capacity estimates cluster around 320,000 wafers per month now, rising toward roughly 420,000 by 2027; more aggressive commentary talks about 500,000 by 2028. TrendForce’s read is that the extra wafers mostly backfill China’s standard DRAM imports (DDR5, LPDDR5) as the Big Three starve those lines for HBM, and that China’s own AI and cloud build can absorb the increment through 2027. [20] [21] [22]

HBM is where the gap is still a generation. Reuters reported on October 28, 2026 that CXMT has sampled HBM3E to domestic AI chip designers and plans limited production within about two months, at yields of roughly 20–30% versus about 70% at SK hynix. Samsung and SK hynix are already in HBM4 volume, with HBM4E mass production targeted for 1H27 at Samsung. Even a successful CXMT ramp leaves China on HBM3E while the export market is qualifying HBM4. In late October CXMT also claimed engineering-sample validation of a 4F² DRAM platform and said it would sample server DDR5 RDIMMs by year-end; mass-production yield is unproven, and Micron has reportedly declined to commercialize 4F² on yield grounds. [20] [23] [24]

YMTC is the volume threat, and it is in NAND. Counterpoint put YMTC at 16.5% of global NAND shipments in 2Q26, third worldwide; Omdia put its China NAND share at 38.5%, ahead of Samsung. Current output is about 200,000 wafers per month across two Wuhan fabs. Fab 3 starts late 2026 and ramps in 2027. Omdia’s wafer forecast is 2.01 million wafers in 2026 to about 2.50 million in 2027, an increase several times larger than Samsung’s or SK hynix’s planned NAND adds, because the Koreans are spending on DRAM/HBM. Fabs 4 and 5 are each talked about at roughly 100,000 wafers per month when full; Fab 4 construction is expected in 2027, aimed at >300-layer NAND with 60–70% domestic tools. The long-term company target cited in market commentary is about 500,000 wafers per month including a DRAM side-bet. That DRAM side-bet is still a pilot: LPDDR5 at about 5,000 wafers per month in test since late 2025, with trial production discussed as early as end-2026, and a faster 4F²/VCT version not yet in mass production. An IPO sized around $4.9 billion has slipped into 1H27. [21] [25] [26] [27] [28]

Export controls shape this, they do not freeze it. The December 2024 BIS rule (ECCN 3A090.c) controls HBM above a memory-bandwidth-density threshold and reaches foreign-produced HBM via the Foreign Direct Product rule, so Korean and US HBM cannot be sold into Chinese accelerators in the normal channel. CXMT is not on the BIS Entity List; it is on the Defense Department’s 1260H list, which is a procurement and reputational mark, not an Entity List licensing ban. The practical result is a captive Chinese customer that will buy 20–30% yield HBM because the alternative is the gray market. Smuggled HBM3E has been reported around $4,000 per stack, and a co-packaged loophole—packages whose primary function is compute are judged on the processor, not the memory—has been used to move HBM inside server modules. Huawei and other domestic accelerator vendors have raised chip prices on memory cost. The September 2026 US-China summit left advanced-chip and tool controls in place. Controls therefore slow CXMT’s yield curve (no EUV, restricted bonders and metrology) while guaranteeing it a domestic order book. They do not create a global HBM surplus. [29] [30] [31] [32]

For a non-Chinese buyer, CXMT is a 2027–28 pressure valve on commodity DDR/LPDDR inside China, not a qualified second source for HBM4. YMTC is the name that can soften NAND contract prices a year or two before DRAM turns.

CoWoS expands fast and still does not free memory

TSMC’s advanced packaging is a parallel bottleneck, not a substitute for DRAM wafers. Published capacity figures disagree on the exact level and agree on the slope:

• End-2026: TSMC roughly 120,000–140,000 CoWoS wafers per month, with industry totals near 160,000–200,000 once OSATs are included.
• 2027: TSMC targets cited around 180,000–200,000; KGI has raised its end-2027 TSMC forecast to 185,000–190,000 and still sees a 15–20% gap versus revised customer demand. UBS has talked about industry CoWoS near 270,000 by end-2027, with ASE’s increment more aggressive than TSMC’s.
• 2028: street figures around 260,000 for TSMC, Yole nearer 270,000. One supply-chain account allocates about 60% of that to Nvidia. [33] [34] [35] [36] [37]

TSMC has said CoWoS capacity compounds above 80% a year from 2022 to 2027. That still only keeps pace with AI accelerator wafer demand, and package size is eating the gain. CoWoS-L is moving toward roughly 9 to 9.5 reticle equivalents in 2027; only a handful of those interposers fit on a 300 mm wafer, versus a dozen or more of today’s smaller packages. NVIDIA Rubin Ultra-class designs stack on the order of 16 HBM cubes in one socket. Wafer-per-month headlines therefore overstate chip throughput. TrendForce-linked reporting has TSMC and OSATs weighing another 10–20% CoWoS price increase, with equipment lead times out to about eight months. Meaningful non-Taiwan relief—Amkor in Arizona, GlobalFoundries interposers for TSMC—is an early-to-mid-2028 event. TSMC’s panel-level CoPoS is a 2028 start with meaningful volume more like 2029. Intel’s EMIB-T is the credible second source being shopped to hyperscalers, not a 2026 release valve. [38] [39] [40] [41]

Implication: even if HBM bits loosen in 2028, accelerator shipments can stay packaging-constrained. A memory glut and a CoWoS glut are different events. CoWoS expansion supports HBM demand; it does not create spare DDR5.

The 2029 oversupply case, and what it assumes

There is no single published house forecast that treats a 2029 DRAM glut as the base case. The date shows up as the first year the announced greenfield stack can reach balance, and as the year equity markets are already discounting.

The most explicit supply-side dating is an October 2026 Aephel sector note (an AI-authored research desk piece, not a bank): announced fabs add on the order of 1.9 million wafers per month of DRAM capacity across 2026–30, including about 475,000 at CXMT, 360,000 at SK hynix Yongin, and 420,000 across Samsung P4/P5. On those schedules the market reaches balance in 2029 and a modest surplus in 2030. Its demand assumption is DRAM bit demand at a 21% CAGR to 2030, with servers at 43% and HBM bits at 39%. It has demand/supply at 108–112% through 2026–28. A stress case in which China reaches 25% of DRAM by 2030 pulls the surplus forward to 2029 and cuts 2030 incumbent DRAM profit by about 30%; the authors treat 25% as plausible in NAND and not in DRAM without a 4F² or 3D-DRAM breakthrough. [42]

That sits against a tighter near-term tape:

• TrendForce, via an October 2026 Goldman memory expert conference: DRAM stays tight through 2027, the price upcycle extends into 1H28, and meaningful new capacity is hard before 2028 because of cleanroom space and tool lead times. HBM blended ASP was projected up about 122% year over year in 2027, to about $3.7 per gigabit, with HBM industry revenue above $200 billion. Each Korean supplier was seen adding only 80,000–100,000 wafers per month by 2027, much of Samsung’s add going to HBM, so conventional bit growth depends on node migration. [43]
• Citi in early November 2026 still has 2027 undersupplied, but narrowed the DRAM gap to −3.8% from an earlier −8.7%, with supply bit growth of 24% against demand of 28%. A September Citi note had been more aggressive, arguing continual-learning workloads could widen the gap in 2028 and stretch the shortage to 2031, with 2027 DRAM wafer capacity up only about 8% in one Korean press account of that work. The November revision is the more current number; the 2031 call is a demand scenario, not a capacity fact. [44] [45] [46]
• CSIS (September 2026): the capex required to end today’s shortage can recreate the next glut if AI demand slows while Samsung, SK hynix, Micron, and China all ramp together—a replay of past memory “chicken” cycles. If AI demand keeps growing at recent rates, the same wafers are absorbed. A new memory fab still costs roughly $15–20 billion and two to three-plus years. [9] [47]
• Company guidance is the high end of tightness: SK hynix through 2030, Samsung into 2028, Micron explicitly tighter in 2027–28 than in 2026. Deloitte’s July 2026 view was that new supply does not really arrive until 2029 or 2030. Nvidia’s CFO has framed memory constraints as weighing on growth at least through the end of fiscal 2028. [6] [48] [8]

The assumptions that have to hold for a 2029 balance, rather than a 2028 collapse or a 2031 shortage, are therefore:

1. Bit growth decelerates but does not break. Near-term demand in the mid-20s to about 30% (Citi’s 28% for 2027 DRAM) has to slow toward something closer to Aephel’s 21% CAGR by the end of the decade. Node migration no longer delivers “free” bits the way older shrinks did, so wafer adds have to do the work.
2. Capex is large but lagged. Producers are not showing classic discipline—they are accelerating shells—but cleanroom and tool lead times insert 18–30 months between the decision and sellable bits. LTAs covering half to 70% of 2027–28 output also reduce the incentive to flood the spot market. The glut risk is simultaneous 2028–30 ramps, not 2026 capex prints.
3. HBM yield stays a tax on wafers. At ~70% mature yield and a 3–4× area penalty, 30% of wafers still produce only low-teens bit share. A faster yield climb on 12-high and 16-high HBM4 would release conventional bits earlier than the 2029 models assume. CXMT at 20–30% does the opposite for global supply: it consumes Chinese wafers without exporting competitive HBM.
4. China stays mostly domestic through 2028. TrendForce’s absorption thesis has to fail—CXMT DDR5 or 4F² qualifying at non-Chinese hyperscalers in volume—before China alone pulls a DRAM surplus forward.

A Korean press column and some market commentary have flagged 2029 as the year new supply turns competitive, and one secondary account has DRAM prices down about 23% in 2028 versus 2027 while still far above 2025. That is a peak-and-fade, not a glut. The 2029 date in serious work is a balance year under full execution of announced fabs, with a modest surplus more naturally in 2030.

Supply-demand timeline

Year	Supply that actually shows up	Demand / pricing signal	Balance
2026	HBM ~22% of DRAM wafers, ~9% of bits. M15X starting. CXMT HBM3E sampling at poor yield. TSMC CoWoS ~120–140k wpm.	Sold out on HBM; Korean inventories reportedly under 10 days. LTAs being written through 2028–29.	Deep shortage. Commodity DRAM starved by HBM mix.
2027	Partial only: Micron ID1 and Tongluo mid-year, Singapore HBM packaging early, SK Y1 cleanroom from February with limited wafers, Samsung HBM starts toward ~250k/month, CXMT toward ~420k mostly for China, YMTC Fab 3 ramp. HBM ~30% of wafers / ~13% of bits. CoWoS toward ~180–200k at TSMC, still short on large packages.	Citi: DRAM demand +28%, supply +24%, gap about −4%. Samsung and Micron: tighter than 2026. TrendForce: HBM ASP roughly +120% YoY.	Still short. First year of greenfield wafers, not a relief year.
2028	First broad wave: Samsung P5, Micron ID2 / Hiroshima / Singapore NAND, SK Y1 in real ramp, Micron Taiwan EUV fab. Tooling conditions improve from 2H27, so this is the first year new shells matter. Some CoWoS relief outside Taiwan.	TrendForce: price upcycle into 1H28, then the open question. Micron: still tighter than 2026. Aephel: DRAM peaks around 2Q28; NAND contract down 15–25% as the more likely soft spot.	Shortage easing at the margin in 2H, not a glut, unless AI capex stalls. NAND can loosen before DRAM.
2029	Overlap year: SK Y2 cleanroom (June), Samsung Yongin first fab targeted, Y1 further up the ramp curve, CXMT’s multi-year add largely in place. Micron New York still ~2030. CoPoS starts to matter.	Base case in the explicit wafer-add model: balance. Company guidance (SK hynix) still says shortage if AI demand holds. LTAs blunt a price collapse even if bits loosen.	Candidate balance year. Modest surplus is a 2030 story unless China or demand breaks.
2030–31	SEMI: DRAM capacity +41% vs 2025. Yongin and Pyeongtaek clusters plus Micron New York in ramp. Full run-rate of shells announced in 2025–26.	SK hynix and some demand scenarios (continual learning, physical AI) still short. CSIS: this is when a classic overbuild can show up if 2026–28 capex all lands and AI growth slows.	Decision year for the next downcycle. Capex can still be slipped; the shells will already exist.

Confidence is high on 2026–27 tightness, because it is in company disclosures and contract coverage. Confidence is medium on 2028 as an inflection rather than a collapse. Confidence is low on the exact quarter of balance in 2029–30, because it depends on HBM yield, China qualification, and hyperscaler capex three years out.

What would pull a glut forward of 2029

An earlier glut means surplus bits in 2027 or 2028, not a softer print in 2030. Six triggers would do it, in rough order of how fast they could hit.

1. An AI capex air pocket, not a slowdown in the narrative. Aephel’s sensitivity is the sharpest published one: DRAM stays short in 2027 only if top hyperscaler capex grows more than about 25%; flat capex implies roughly a 10% surplus that year. JPMorgan has flagged about 37 GW of US data-center capacity scheduled for 2028 as exposed to permitting risk. That matters only if it cancels memory orders already in LTAs, rather than sliding builds to other regions. Watch take-or-pay renegotiations, not headline capex guidance. [42] [49]
2. HBM yield jumping faster than the 3–4× wafer tax. If 12-high and 16-high HBM4 yields move well through the current ~70% mature level, the same wafer start produces more sellable stacks and frees DDR5. The opposite—yields stuck, customers already de-specing Rubin Ultra from 12-high toward 8-high—keeps the shortage. De-spec is rationing, not demand destruction, unless content per GPU falls faster than unit growth.
3. CXMT qualifying outside China. A 4F² or mainstream DDR5 RDIMM that hyperscalers will buy in volume, or HBM yields moving from the 20–30% range toward 50% with a product that can leave China, is the supply shock that pulls a commodity-DRAM surplus into 2028–29. Domestic absorption through 2027 is the reason this has not happened yet. Export controls make the HBM version of this shock slower, not impossible.
4. Tool lead times collapsing. If the six-to-eight-month equipment queue shortens and every 2028 shell (P5, ID2, Hiroshima, Y1 phases) ramps in the same two quarters without utilization cuts, the historical memory pattern returns: supply decisions made at the peak arrive together. Producers say they will pace this. They have said that before.
5. LTA breakage. Contracts covering 50–70% of 2027–28 output are the earnings floor. If cloud buyers force price resets or volume cuts when spot softens, the floor becomes the transmission mechanism for a glut rather than a cushion. Deposits and market-linked pricing at SK hynix are designed to prevent exactly that.
6. NAND first, then DRAM by contagion. YMTC’s 2027 wafer add, against Korean NAND capex deferred toward HBM, can put NAND into surplus in 2027–28 even while DRAM is tight. If enterprise SSD pricing breaks and hyperscalers reallocate budgets, DRAM contract negotiations in late 2027 feel it before any new DRAM fab is full. That is the earliest plausible “glut,” and it is a NAND glut.

The competitive implication is asymmetry. Incumbents have sold the shortage forward and are building the capacity that could end it in 2029–30. A new entrant or a buyer betting on cheap DRAM in 2027 is fighting cleanroom physics and a 3× HBM wafer penalty. A buyer who needs NAND, or a Chinese commodity DRAM alternative for non-HBM uses, has a real supply response arriving sooner. The trigger list above is the monitoring set: hyperscaler capex revisions, HBM4 yield commentary, CXMT qualification wins outside China, and whether 2028 tool move-ins are pulled in or quietly slipped.

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Recent Findings Supplement (November 2026)

Micron has paused its key Taiwan HBM/DRAM expansion while accelerating Singapore and US sites, creating near-term supply uncertainty amid strong contracted demand.[1][2]

• In early November 2026 reports, Micron effectively halted construction on the $4.5 billion Fab 11E in Taoyuan (intended for EUV-based 1-gamma DRAM and HBM, with 2028 startup) due to a labor dispute with the Taoyuan union over profit-sharing bonuses and pay terms; minor safety work continues but major activity has stopped, with no resumption timeline disclosed. This follows an October agreement with the larger Taichung union.[3][4]
• Offsetting this, Micron confirmed progress on a $7 billion Singapore HBM advanced packaging facility (first outside Taiwan), with initial output targeted for early 2027, plus a $24 billion double-story wafer fab slated for 2H 2028 operations.[5][6]
• The company also announced a January 16, 2027, groundbreaking for its $100 billion New York megafab campus (up to four fabs, advanced memory for AI).[7]
• In Taiwan, the second advanced assembly/test facility (AATT2) in Taichung opened in mid-October 2026; HBM output through 2027 is fully contracted. Tongluo (acquired from PSMC, closed March 2026) targets mid-2027 wafer shipments.[8][9]
• A $9.3 billion Hiroshima expansion (announced earlier but with ongoing relevance) adds cleanroom space for 1-gamma/1-delta DRAM and HBM4E, with 2028 production.[10]

This mix of delays in Taiwan and acceleration elsewhere signals Micron prioritizing diversified, geopolitically resilient capacity while facing execution risks from labor issues; competitors may gain share if the pause extends.[11]

SK hynix and Samsung report near-total sellouts of DRAM/HBM capacity through 2028–2029 via long-term agreements (LTAs), with explicit expectations of shortages persisting into 2030.[12][13]

• On its October 28, 2026, Q3 earnings call, SK hynix stated that DRAM and HBM volumes are “effectively sold out” through 2029 when combining secured LTAs (with 14 customers, covering >50% of 2027–2028 capacity) and ongoing negotiations; customer HBM requests exceed twice current supply. It expects shortages to continue through 2030 due to fab lead times and process complexity. HBM4 is projected to surpass HBM3E in Q4 2026 shipments/revenue; M15X fab ramps to full capacity by year-end.[14][15][16]
• Samsung’s October 29, 2026, Q3 call confirmed 2027 HBM supply fully sold out (with ongoing additional requests); HBM4 revenue more than tripled QoQ. It signed LTAs with 10 major customers, is negotiating with 10 more, and targets 60–70% capacity coverage by 2030. HBM4E mass production begins H1 2027. Overall memory supply expected tight through 2028; record 2026 capex of 84.4 trillion won (mostly semiconductors).[17][18][19]
• Both companies note stable or improving HBM4 yields and pricing power from the tight market.

These sellouts and multi-year visibility via LTAs (with deposits and flexible pricing) lock in revenue and reduce cyclical risk, but they also highlight how capacity additions are lagging AI-driven bit demand; new entrants or Chinese players face high barriers to displacing contracted supply.[20]

Chinese players CXMT and YMTC are advancing despite technology gaps, with CXMT targeting limited HBM3E output by end-2026 at low yields and YMTC scaling NAND while eyeing DRAM.[21][22]

• Reuters reported October 28, 2026, that CXMT plans limited HBM3E production within two months (by ~end-2026), having shipped samples to domestic AI chip designers; yields are estimated at 20–30% (vs. SK hynix ~70%), with performance closer to prior-generation HBM3. The firm claims progress on high-aspect-ratio TSV processes. Q3 DRAM market share reached ~9–10%. It validated a 4F² DRAM platform and plans DDR5 RDIMM samples by end-2026.[23][24][25]
• YMTC (No. 3 globally in NAND by volume in recent data) filed for a Shanghai STAR IPO and is planning a fourth Wuhan fab (>300-layer NAND, AI/data-center focus) with construction targeted for 2027 and 60–70% domestic equipment (up from ~50%+ at Fab 3). Potential per-fab capacity ~100k wafers/month. It is also conducting R&D on LPDDR5/DRAM using Xtacking/VCT 4F² architectures.[26][27]

Low yields and process immaturity limit near-term impact on global supply, but domestic Chinese demand (and potential indirect channels) could absorb output; export controls add friction but have not fully halted technology leakage.[28]

TSMC is aggressively expanding CoWoS advanced packaging capacity (critical for HBM stacking with logic dies), targeting a doubling by 2028 amid price pressure and allocation battles.[29]

• Analysts (Economic Daily News, Goldman Sachs, etc.) project TSMC CoWoS at ~130k wafers/month by end-2026, rising to ~200k in 2027 and 260k by end-2028 (some estimates higher at ~270–290k). Expansions center on AP7 (Chiayi) and AP8 (Tainan), with US Arizona packaging also planned.[30][31]
• Reports from late October 2026 indicate potential 10–20% CoWoS price hikes due to equipment lead times stretching to 6–8 months and strong AI/ASIC demand. Allocation estimates include ~60% to Nvidia.[32][33]

Packaging remains a key bottleneck alongside HBM; faster CoWoS ramps or rival technologies (e.g., Intel EMIB) could ease constraints, but current trajectories support continued tightness.[34]

Published outlooks emphasize prolonged memory shortages rather than oversupply around 2029, driven by AI bit growth outpacing capacity additions.[35]

• SK hynix (Oct 2026) projects demand exceeding supply through 2030, citing long fab lead times and leading-edge process complexity; LTAs provide visibility but leave limited spot capacity. Micron and Samsung align on tightness into 2028.[36][37]
• Assumptions behind tightness (vs. potential glut): Strong AI-driven bit growth (HBM requiring 3–4x wafer capacity per bit vs. conventional DRAM); disciplined but lagged capex; improving but still-constrained HBM yields; and demand from hyperscalers/cloud/ASICs absorbing supply. Earlier Goldman notes projected undersupply persisting into 2028. No major 2029 glut forecasts appear in recent coverage; instead, extensions of the supercycle are highlighted.[38]

An earlier glut could be triggered by sharper-than-expected slowdown in AI capex, breakthrough yields or faster ramps from Chinese suppliers (CXMT/YMTC), or accelerated global capex leading to oversupply post-2028 once new fabs (e.g., Micron NY/Singapore, Samsung Texas, SK expansions) come online in volume.[39]

Export controls continue to constrain advanced HBM flows to China while prompting workarounds and license requests for maintenance at legacy fabs.[40]

• US rules (including December 2024 HBM controls) remain in effect; SK hynix sought Commerce licenses in October 2026 for Wuxi DRAM equipment maintenance (site produces ~48% of its DRAM). Indirect channels reportedly allow some Korean HBM to reach Huawei-linked supply chains despite bans.[41][42]

Controls raise costs and uncertainty for Korean/Japanese/Taiwanese supply chains but reinforce the premium on non-Chinese advanced capacity for Western customers.[28]

Overall supply-demand timeline (synthesized from recent company guidance and analyst estimates): Tight/shortage conditions through 2026–2028 (with HBM particularly constrained); gradual capacity additions ramping in 2027–2028 but unlikely to close the gap fully until after 2029–2030 absent major demand shifts. Chinese domestic supply grows but at lower yields/efficiency. No credible recent sources forecast a 2029 glut; the dominant view is extended tightness.